Patent · US Active

SRAM memory cell and SRAM memory with conductive interconnect

US10411018B2 · kind B2 · utility

0Cited by

2References

20Claims

0Family size

Assignee

Semiconductor Manufacturing International Corp. · CN

Inventors

Tzu-Yin Chiu · Marlboro, US
JUILIN LU · Shanghai, CN
Jianxiang Cai · Shanghai, CN

Key dates

Filing date	May 12, 2016
Grant date	Sep 10, 2019
Priority date	—
Expiry date	Dec 21, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH10D89/10
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Various embodiments provide semiconductor structures and their fabrication methods. An SRAM memory cell can include at least one semiconductor structure, and an SRAM memory can include at least one SRAM memory cell. An exemplary semiconductor structure can include at least two adjacent transistors formed on a semiconductor substrate. An opening can be formed and surrounded by gates of the two adjacent transistors and a doped region formed between the gates of the two adjacent transistors. A conductive layer can be formed to at least partially cover a bottom and a sidewall of the opening to electrically connect a gate of one transistor with the doped region of the other transistor of the two adjacent transistors.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.