Integrated circuit memory devices having impurity-doped dielectric regions therein and methods of forming same
US10411034B2 · kind B2 · utility
1Cited by
7References
20Claims
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Key dates
| Filing date | Jun 7, 2018 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Jun 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.