Semiconductor memory device and method of manufacturing the same
US10411137B2 · kind B2 · utility
0Cited by
3References
2Claims
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Assignee
Inventor
Key dates
| Filing date | Nov 28, 2016 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Dec 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor device, which prevents unnecessary voltage drop in a MOS transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the ON/OFF ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.