Device and method for multiple reference system timer
US10411717B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 2016 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Sep 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/40
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device and method is presented to allow the high frequency clock generators and functional blocks of a wireless communication device to enter a very low power sleep state while the low frequency reference clock generator within the wireless communications device remains in an active state. The timing block provides methods of increasing and maintaining accuracy of the system timer which may have been reduced by temperature variation or manufacturing defects. The timing block also allows for selection of the highest accuracy clock from among multiple high frequency clock references. A device for timing control is presented comprising at least one high frequency reference clock, a low frequency reference clock and a timing controller for generating a system timer, wherein the timing controller selects one of the at least one high frequency reference clock and processes the low frequency reference clock with the selected high frequency reference clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.