Phase-locked loop output adjustment
US10411718B2 · kind B2 · utility
0Cited by
5References
26Claims
0Family size
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Key dates
| Filing date | Sep 25, 2017 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Mar 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.