High throughput hardware unit providing efficient lossless data compression in convolution neural networks
US10411727B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2018 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Oct 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1117
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a first memory interface circuit, a second memory interface circuit, and a compression circuit coupled between the first memory interface circuit and the second memory interface circuit. The compression circuit may be configured to receive a coding block of data via the first memory interface circuit, generate a reduced size representation of the coding block, and write the reduced size representation of the coding block to an external memory using the second memory interface circuit. The reduced size representation of said coding block generally comprises a first bit map, a second bit map, and zero or more non-zero values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.