Hierarchical queue scheduler
US10412018B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2017 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Aug 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/324
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide a method for scheduling a packet to be dequeued to a processing pipeline of a hardware forwarding element. The method selects a node representing one of multiple ports associated with the processing pipeline. For each of one or more layers of logical queues, the method (i) identifies a set of logical queue nodes associated with a previously selected node based on a configuration that maps multiple physical queues to the multiple ports via the one or more layers of logical queues and (ii) selects one of the identified logical queue nodes based on properties of the identified logical queue nodes. The method selects one of a set of physical queues associated with a selected logical queue node of the last layer of logical queues. The method dequeues a next packet from the selected physical queue for processing by the processing pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.