Array substrate and method of fabricating the array substrate
US10416506B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2017 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Jun 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present application discloses an array substrate, including a substrate; a thin film transistor disposed on the substrate; a pixel electrode disposed on the substrate and is in contact with a drain electrode of the thin film transistor; a common electrode disposed above the pixel electrode and is electrically insulated from the pixel electrode, and the common electrode has a plurality of first through holes. The present application further discloses a method of fabricating the array substrate. The array substrate and the fabricating method of the present application can reduce the parasitic capacitance between the common electrode and the pixel electrode, and can accelerate the release of the aggregated ions. In addition, the present application, by forming a stereoscopic electrode structure, the lateral electric field can be effectively enhanced, so that the driving voltage can be reduced, the display transmittance can be improved, and the power consumption can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.