Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses
US10417002B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2017 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Oct 19, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technical solutions are described for hazard detection of out-of-order execution of load and store instructions without using real addresses in a processing unit. An example includes an out-of-order load-store unit (LSU) for transferring data between memory and registers. The LSU detects a store-hit-load (SHL) in an out-of-order execution of instructions based only on effective addresses by: determining an effective address associated with a store instruction; determining whether a load instruction entry using said effective address is present in a load reorder queue; and indicating that a SHL has been detected based at least in part on determining that load instruction entry using said effective address is present in the load reorder queue. The LSU, in response to detecting the SHL, flushes instructions starting from a load instruction corresponding to the load instruction entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.