System, method, and computer program product for debugging in an electronic design file
US10417361B1 · kind B1 · utility
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17Claims
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Key dates
| Filing date | Apr 21, 2017 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Sep 1, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure may include receiving, using a processor, an ASCII file including timing and power parameters associated with a portion of the electronic circuit design. Embodiments may further include analyzing the ASCII file and displaying, at a graphical user interface, information from the ASCII file. Embodiments may also include parsing, via the graphical user interface, the information using one or more user-selectable parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.