Systems and methods for reducing power consumption of latch-based circuits
US10417365B1 · kind B1 · utility
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Key dates
| Filing date | Sep 21, 2018 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Sep 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example circuit includes: a first clock gating circuit coupled between a first latch and a second latch and configured to provide a first gated clock signal based at least in part on an input clock signal. The first latch is configured to be activated in response to the first gated clock signal being at a first logic level to pass a data input. The second latch is configured to be activated in response to the input clock signal being at a second logic level to pass a first selection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.