Graphics hardware bottleneck identification and event prioritization
US10417729B2 · kind B2 · utility
1Cited by
3References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2016 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Mar 3, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques to sort events of a graphics workload executed by a graphics processing unit to provide identification of events, that if addressed, may result in an improvement in performance are disclosed. The techniques can include: generating a signature and a weight for each event of a graphics workload; generating an event priority tree by organizing the events into parent and leaf nodes, where parent nodes comprise leaf nodes having a shared hash; and sorting frames based on a global weight of events corresponding to the frames.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.