Read assist circuit with process, voltage and temperature tracking for a static random access memory (SRAM)
US10418095B2 · kind B2 · utility
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1References
18Claims
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Assignee
Inventor
Key dates
| Filing date | May 14, 2018 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | May 14, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node. A bias circuit applies a biasing voltage to the gate terminal of the n-channel pull-down transistor that is modulated responsive to process, voltage and temperature conditions in order to provide controlled word line underdrive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.