Patent · US Active

Bypass circuitry for memory applications

US10418124B1 · kind B1 · utility

0Cited by

3References

17Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Vivek Asthana · Greater Noida, IN
Nitin Jindal · Noida, IN
Saikat Kumar Banik · Noida, IN

Key dates

Filing date	Feb 23, 2018
Grant date	Sep 17, 2019
Priority date	—
Expiry date	Feb 23, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/848
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to an integrated circuit having core circuitry with an array of bitcells arranged in columns of bitcells that may represent bits. A first column of bitcells may represent a nearest bit of the bits, and a last column of bitcells may represent a farthest bit of the bits. The integrated circuit may include sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells. The integrated circuit may include multiplexer circuitry coupled to the sense amplifier circuitry. The integrated circuit may include first bypass circuitry coupled to outputs of the sense amplifier circuitry at the farthest bit. The integrated circuit may include second bypass circuitry coupled to an output of the multiplexer circuitry at the nearest bit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.