Write and read common leveling for 4-bit wide DRAMs
US10418125B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 2018 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Jul 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System and method of write deskew training for ×4 mode memory control interface configurations. Write leveling logic in the memory controller is adjusted to obtain a write leveling setting for delaying both first and second strobe signals associated with a byte. The adjustment is based on feedback of first set of bits of a byte and irrespective of the feedback of the second set of bits of the byte. The write leveling logic is then anchored at the write leveling setting, and a deskew delay line for the second strobe signal is adjusted to obtain a first deskew setting based on the feedback of the second set of bits. Thus, in write operations, the write leveling setting can be common within the byte even the two strobe signals are transmitted to or received from two different memory storage devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.