Patent · US Active

Method and apparatus for using universal cavity wafer in wafer level packaging

US10418249B2 · kind B2 · utility

0Cited by
9References
15Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 19, 2017
Grant dateSep 17, 2019
Priority date
Expiry dateDec 19, 2037

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/3511
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

An electronics module assembly is described herein that packages dies using a universal cavity wafer that is independent of electronics module design. In one embodiment, the electronics module assembly can include a cavity wafer having a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer and a plurality of fillports. The assembly can also include at least one group of dies placed in the frontside cavity and encapsulant that secures the position of the at least one group of dies relative to the cavity wafer. Further, a layer of the encapsulant can cover a backside of the cavity wafer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.