Electronic assembly with a direct bonded copper substrate
US10418307B2 · kind B2 · utility
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2References
22Claims
0Family size
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Key dates
| Filing date | Dec 22, 2017 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Dec 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metallic island is disposed between a first metallic bus and a second metallic bus. The first metallic strip is isolated from the metallic island by a first dielectric barrier. At least a parallel portion of the first metallic strip is generally parallel to the first metallic bus, the second metallic strip isolated from the second metallic bus by a second dielectric barrier. Each first semiconductor terminals that are coupled to the first metallic bus and to the metallic island. Each second semiconductor has terminals coupled to the metallic island and to the second metallic bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.