Fan-out semiconductor package
US10418317B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2018 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Jul 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a first recess portion and a first stopper layer disposed on a bottom surface of the first recess portion; a semiconductor chip disposed in the first recess portion and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the first stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the first recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.