Electronic packages with three-dimensional conductive planes, and methods for fabrication
US10418344B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | Jan 26, 2018 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Jan 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06565
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package includes an adhesion layer between a first substrate and a second substrate. The adhesion layer is patterned to define openings aligned with through-substrate interconnects and corresponding bond pads. A conductive plane is formed between the first substrate and the second substrate, adjacent to the adhesion layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.