Integrated circuit and computer-implemented method of manufacturing the same
US10418354B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2018 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | May 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53295
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit, selecting a timing critical path from among a plurality of timing paths included in the placed standard cells, and selecting at least one net from among a plurality of nets included in the timing critical path as at least one timing critical net. The method further includes pre-routing the at least one timing critical net with an air-gap layer, routing unselected nets, generating a layout using the pre-routed at least one timing critical net and the routed unselected nets, and manufacturing the integrated circuit based on the layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.