Switching regulator including an offset enabled comparison circuit
US10418896B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 2018 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Jul 11, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A switching regulator includes: an error amplification circuit configured to amplify a difference between a voltage based on the output voltage and a first reference voltage to output an error voltage; a PFM comparison circuit configured to compare the error voltage with a second reference voltage to output a comparison result signal at a first level or a second level, an offset being given to the error voltage for a given period in response to a change of the comparison result signal from the second level to the first level; an oscillation circuit configured to output a clock signal of a given frequency according to the first level of the comparison result signal, and to stop outputting the clock signal according to the second level of the comparison result signal; and a PWM conversion circuit configured to turn the switching element on at a prescribed pulse width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.