Adaptive body biasing in CMOS circuits to extend the input common mode operating range
US10418989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2018 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Oct 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.