Level shifter
US10418997B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 29, 2017 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Nov 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Between a power supply potential and a reference potential, a first PMOS transistor and a first NMOS transistor are connected in series via an inverting output node and a second PMOS transistor and a second NMOS transistor are connected in series via a non-inverting output node. A third NMOS transistor is connected in parallel to the first NMOS transistor and a fourth NMOS transistor is connected in parallel to the second NMOS transistor. A gate of the first PMOS transistor and a gate of the third NMOS transistor are connected to the non-inverting output node and a gate of the second PMOS transistor and a gate of the fourth NMOS transistor are connected to the inverting output node. The first and second NMOS transistors receive a non-inverted signal and an inverted signal of an input signal at their gates, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.