Digital frequency-division phase-locked loop
US10419007B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 24, 2018 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Oct 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital frequency-division phase-locked loop, including a time-to-digital converter (TDC), a digital loop filter (DLF), a digital-controlled oscillator (DCO), a feedback frequency divider (DIV), a sigma-delta modulator (SDM), and a calibration apparatus, where the calibration apparatus compensates for, based on a frequency control word and a frequency-division control word generated by the SDM, a digital signal output by the TDC to obtain a calibration signal. The DLF performs digital filtering on the calibration signal to obtain an oscillator frequency control signal and set the oscillator frequency control signal as an output signal of the DCO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.