Peak/bottom detection circuit, A/D converter, and integrated circuit
US10419012B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 15, 2018 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Oct 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2481
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A peak/bottom detection circuit is disclosed. A comparator compares a voltage of one of three or more capacitors with an input voltage. A calculation amplifier amplifies the voltage of one of the three or more capacitors. Each of three or more switches respectively corresponding to the three or more capacitors connects a corresponding capacitor among the three or more capacitors to one of the comparator, the calculation amplifier, and a source of the input voltage. A controller generates control signals for sequentially switching connection destinations of the three or more capacitors and to supply the control signals to the three or more switches, respectively, in which the connection destinations of three capacitors among the three or more capacitors are different from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.