Enforcing power caps on computing devices with multiple power feeds
US10423204B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2017 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Nov 23, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism is provided for enforcing power caps within a power consumption device with multiple power supplies. Utilizing a minimum power error value from a set of error values, the minimum power error value is multiplied by a factor k to translate the minimum power error value to an internal power error value. The internal minimum power error value is multiplied by a number of working power supply units (M) of the power consumption device, resulting in an internal minimum power error value for multiple power supply units. The internal minimum power error value for the multiple power supply units is summed with a present power cap value thereby forming a summed power cap value. Responsive to the summed power cap value being between a power cap maximum and a power cap minimum, the computing load is throttled using the summed power cap value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.