FIFO circuit for DDR memory system
US10423386B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2018 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Jun 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A FIFO circuit for a DDR memory system includes a pointer generator and a FIFO circuit. The FIFO circuit includes a pointer generator and a FIFO buffer. The pointer generator receives a first reset signal and a delay select signal from the memory controller. After the first reset signal is de-asserted, the pointer generator generates a write pointer according to a first reference clock and the pointer generator generates a read pointer according to a second reference clock. An input data is stored into the FIFO buffer according to the first reference clock and the write pointer. An output data is outputted from the FIFO buffer according to the second reference clock and the read pointer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.