Apparatus and method for predicting a redundancy period
US10423510B2 · kind B2 · utility
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Key dates
| Filing date | Oct 4, 2017 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Dec 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprises a plurality of memory units organized as a hierarchical memory system, wherein each of at least some of the memory units is associated with a processor element; predictor circuitry to perform a prediction process to determine a predicted redundancy period of result data of a data processing operation to be performed, indicating a predicted point when said result data will be next accessed; and an operation controller to cause a selected processor element to perform said data processing operation, wherein said selected processor element is selected based on said predicted redundancy period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.