Automatic performance tuning for memory arrangements
US10423525B2 · kind B2 · utility
1Cited by
2References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2018 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Jan 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3476
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arrangement is disclosed comprising a memory arrangement configured to store and retrieve data; an interface to allow data to be received and transmitted by the arrangement from a host and a processor configured to dynamically conduct automatic performance tuning for the memory arrangement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.