Operation processing device, information processing apparatus, and control method for operation processing device
US10423528B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2017 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Aug 18, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes: a processor core to execute an instruction; a first cache to retain data used by the processor core; and a second cache to be coupled to the first cache, wherein the second cache includes a data-retaining circuit to include storage areas to retain data, an information-retaining circuit to retain management information that includes first state information for indicating a state of data retained in the data-retaining circuit, a state-determining circuit to determine, based on the management information, whether requested data that is requested with a read request from the first cache is retained in the data-retaining circuit, and an eviction-processing circuit to, where the state-determining circuit determines the requested data not to be retained in the data-retaining circuit with no enough space in the storage areas to store the requested data, evict data from the storage areas without issuing an eviction request based on the read request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.