Patent · US Active

Reduced resource harmonic balance circuit simulations

US10423744B1 · kind B1 · utility

1Cited by

22References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Joel R. Phillips · Sunnyvale, US
Jun Meng · Bellevue, US
Yunbo Pang · Beijing, CN

Key dates

Filing date	Jan 28, 2015
Grant date	Sep 24, 2019
Priority date	—
Expiry date	Jun 10, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/30
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system, method, and computer program product for reduced resource harmonic balance circuit simulations is disclosed, wherein a lattice structure is implemented in place of conventional approaches in order to reduce the amount of data being processed in each iteration of the harmonic balance process. Additionally, sparse frequency cuts, which correspond to the lattice structures, are disclosed. The sparse frequency cuts and the lattice structure may be may be customized, modified, and/or adjusted to match a variety of circuits with non-linear components, such as those found in microwave, RF, and multicarrier (e.g. LTE) implementations.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.