Display flicker reduction systems and methods
US10424244B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2017 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Jun 12, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/16
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the subject technology relate to electronic devices with displays. A display may include an array of display pixels each having a drive transistor and an organic light-emitting diode. A pulse-width-modulated current may be provided to the organic light-emitting diode during each display frame to compensate for an on-bias compensation applied to the drive transistor between display frames. The pulse-width-modulated current may be provided with a pulse-width-modulation ratio that decreases over the course of each display frame. The decrease of the pulse-width-modulation ratio for each display frame may be determined based on a peak luminance for that display frame. The reduction in flicker provided by the pulse-width-modulated current may facilitate operation of the display with a reduced refresh rate, thereby reducing power consumption by the display.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.