Reduced latency I/O in multi-actuator device
US10424328B1 · kind B1 · utility
10Cited by
10References
20Claims
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Key dates
| Filing date | Apr 25, 2018 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Apr 25, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B5/58
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An exemplary data refresh method disclosed herein reading data into volatile memory from a first storage region using a read element controlled by a first actuator assembly and writing the data from the volatile memory to a second storage region using a write element controlled by a second actuator assembly, where the first actuator assembly and the second actuator assembly are configured to receive data from control circuitry via independent read/write communication channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.