Reduced electrical terminations in surface-mount technology components
US10424438B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Sep 24, 2016 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Mar 8, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Systems and methods described in this disclosure are related to fabrication and utilization of two-terminal electrical components that may have terminations with reduced width. Components, such as the ones described herein may be used to increase the density of components in electrical devices, as they may reduce a separation distance between devices that lead to solder bridging. Methods for fabrication are also described, including the use of ceramic layers that may provide reduction in parasitic capacitance and/or inductances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.