Semiconductor device
US10424575B2 · kind B2 · utility
2Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2015 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Mar 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Based on a basic idea to effectively utilize a space created in a third wiring layer (M3) by a zero-th wiring layer (M0) which can exist by miniaturization of a FINFET, an auxiliary line AL is arranged in the space created in the third wiring layer, and this auxiliary line AL and a word line WL are electrically connected to each other. Thus, a measure (device) based on such new knowledge that rising time of a word line voltage is largely affected by a wiring resistance of the word line is achieved, a high-speed operation in an SRAM using the FINFET is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.