Thin film transistor with a protective layer, and manufacturing method therefor, display panel and display apparatus
US10424667B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2017 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Feb 27, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
Abstract
A thin film transistor with a protective layer is disclosed. The thin film transistor includes an active region (11), a gate insulating layer (12), a gate (13), a source (14) and a drain (15), a passivation layer (16), and a planarization layer (17) that are successively formed on a flexible substrate (10), wherein a protective layer (18) is formed between the passivation layer (16) and the planarization layer (17), and located directly above the active region (11) and the gate (13), and wherein the protective layer is made of metal and covers part of the active region in a direction perpendicular to the gate, the protective layer completely covering a gap between the gate and the source as well as a gap between the gate and the drain, and not completely covering the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.