Fast settling peak detector
US10425071B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 23, 2017 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Nov 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/153
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure describes aspects of a fast settling peak detector. In some aspects, a peak detector circuit includes a first transistor having a gate coupled to an input of the circuit at which a signal is received and a drain coupled to a source of a second transistor. Current may flow in the first and second transistors responsive to the signal. The circuit also includes a third transistor having a gate coupled, via a signal-inverting component, to the input of the circuit and a drain coupled to a source of a fourth transistor. Through an inversion of the signal, other current flowing in the third and fourth transistor can reduce or cancel a frequency component of the current in the first and second transistors. In some cases, this precludes a need to filter the frequency component from an output of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.