Divider-less phase locked loop
US10425086B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2018 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Oct 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45631
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A divider-less phase locked loop (PLL) includes a phase frequency detector (PFD), a charge pump (CP), a voltage controlled oscillator (VCO), a delay unit, and a clock gating unit. The PFD is electrically connected to the VCO through the CP, and the CP outputs a voltage control signal to the VCO. The VCO generates an output signal. The delay unit receives and delays a reference signal to generate a delay signal. The clock gating unit samples the output signal according to the delay signal. Since the clock gating unit samples the output signal according to the delay signal, the divider-less PLL does not need to include a divider to divide a frequency of the output signal. Therefore, power consumption of the divider-less PLL can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.