Fractional clock generator
US10425091B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2018 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Oct 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/22
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A full quadrant analog interpolator used in a fractional clock generator. A quadrature clock signal with minimal jitter is provided to the full quadrant analog interpolator. The full quadrant analog interpolator uses a series of switches and current sources to develop a differential output signal based on a digital input value, thus allowing digital control of the delay developed by the full quadrant analog interpolator. The differential output of the full quadrant analog interpolator is provided to multi-stage comparator. The output of the multi-stage comparator is provided to an integer divider to provide the final output clock. A digital control section utilizes a ΣΔ modulator and a summer to utilize an input N.α control input which provides the desired fractional division amount to provide a signal to a phase accumulator. The output of the phase accumulator is the digital control or β value of the full quadrant analog interpolator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.