Scheduling method of a parity check matrix and an LDPC decoder for performing scheduling of a parity check matrix
US10425104B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2017 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Nov 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6566
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is a method of scheduling a parity check matrix, the method performed by a low-density parity-check (LDPC) decoder, the method including checking at least one non-zero elemental variable node in the parity check matrix, identifying a first index of a row of the parity check matrix in the at least one non-zero elemental variable node, extracting a column in which the at least one non-zero elemental variable node is positionable from the parity check matrix using the first index, and mapping the at least one non-zero elemental variable node to the extracted column based on an arrangement, and identifying a second index of the column of the parity check matrix through the mapped at least one non-zero elemental variable node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.