Test capability-based printed circuit board assembly design
US10430538B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 30, 2017 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Jun 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This application discloses a computing system implementing a schematic capture tool to utilize physical test capabilities of a manufacturer of a printed circuit board assembly during generation of a logical design for the printed circuit board assembly. The schematic capture tool can utilize the physical test capabilities of the manufacturer to trim a list of parts representing electronic components available for use in the printed circuit board assembly, and generate the logical design for the printed circuit board assembly utilized the trimmed list of parts. The schematic capture tool can utilize the physical test capabilities of the manufacturer to determine which nets in the logical design to assign test points. The schematic capture tool can provide an indication of the assigned test points to a layout tool, which can include the test points in a layout design for the printed circuit board assembly based on the assignment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.