Patent · US Active

Methods and apparatus for reducing power consumption in memory circuitry by controlling precharge duration

US10431269B2 · kind B2 · utility

2Cited by

16References

9Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Rajiv Kumar · Hyderabad, IN
Wei Yee Koay · Kampung Bukit Kechil, MY
Kuan Cheng Tang · Bayan Lepas, MY

Key dates

Filing date	Feb 4, 2015
Grant date	Oct 1, 2019
Priority date	—
Expiry date	May 16, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/2227
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Integrated circuits with volatile random-access memory cells are provided. A memory cell may be coupled to write bit lines and a read bit line. The write bit line may not be coupled to any precharge circuitry. The read bit line may only be precharged during memory access operations. In one suitable arrangement, the read bit line may be precharge immediately after an address decoding operation and before an evaluation phase. In another suitable arrangement, the read bit line may be precharged after an addressing decoding operation and in parallel with the evaluation phase. In either arrangement, a substantial amount of leakage and active power can be reduced.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.