Parasitic capacitance compensation circuit
US10431424B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2018 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Dec 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/6875
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a parasitic capacitance compensation circuit for a switch is disclosed that includes a first inductor operably coupled between a first terminal and a second terminal, and a second inductor operably coupled between the first and second terminals and parallel to the first inductor. The second inductor is switched in when a peak voltage on the first and second terminals falls below a first voltage. The first inductance tunes out substantially all of a parasitic capacitance of the switch when the switch is OFF and the peak voltage is above the first voltage. The first and second inductances collectively tune out substantially all of the parasitic capacitance of the switch when the switch is OFF and the peak voltage is below the first voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.