Methods of fabricating semiconductor device
US10431459B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2017 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Nov 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/68764
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An etching target layer is formed on a substrate. An upper mask layer is formed on the etching target layer. A plurality of preliminary mask patterns is formed on the upper mask layer. The plurality of preliminary mask patterns is arranged at a first pitch. Two neighboring preliminary mask patterns of the plurality of preliminary mask patterns define a preliminary opening. An ion beam etching process is performed on the upper mask layer using the plurality of preliminary mask patterns as an etch mask to form a first preliminary-interim-mask pattern and a pair of second preliminary-interim-mask patterns. The first preliminary-interim-mask pattern is formed between one of the pair of second preliminary-interim-mask patterns and the other of the pair of second preliminary-interim-mask patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.