Metal-oxide-metal capacitor with reduced parasitic capacitance
US10431540B1 · kind B1 · utility
2Cited by
1References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 18, 2018 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Jul 18, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/451
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device reduces parasitic capacitance between a metal-oxide-metal (MOM)/metal-insulator-metal (MIM) capacitors and a semiconductor substrate. The semiconductor device includes the semiconductor substrate (e.g., a silicon substrate, a III-V compound semiconductor substrate, or a silicon on insulator (SOI) substrate), a magnetic material layer, and a capacitor. The magnetic material layer is between the semiconductor substrate and the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.