Power-on reset circuit
US10432192B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2018 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Aug 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes an input stage that includes a first transistor device configured to generate a first output signal in response to a first bias current activating the first transistor device by exceeding a first threshold voltage of the first transistor device. A compensation stage includes a second transistor device coupled with a third transistor device. The second transistor device is activated in response to the first output signal exceeding a second threshold voltage of the second transistor device. The third transistor device is activated in response to activation of the second transistor device and a second bias current. The compensation stage is configured to generate a second output signal in response to the activation of the third transistor device. An output stage is configured to generate a reset signal in response to the second output signal exceeding a third threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.