Clock generator
US10432207B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2017 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Dec 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprises an ADC including a first track-and-hold amplifier and a timing generator configured to generate a clock signal for controlling the ADC. The timing generator comprises a quadrature filter responsive to a differential input signal for generating a differential quadrature (I/Q) output signal. The timing generator further comprises at least one first vector sum circuit operatively coupled or connected to an output of the quadrature filter and configured to weight and sum components of the differential I/Q output signal for generating a clock signal having a desired delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.