Open loop solution in data buffer and RCD
US10437279B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2018 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Nov 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a clock tree circuit, a first phase interpolator circuit and a second phase interpolator circuit. The clock tree circuit may be configured to generate a first clock delayed from a system clock by a constant time. The first phase interpolator circuit may be in a calibration loop and configured to generate a second clock with a programmable phase delay relative to the first clock. The programmable phase delay may be controlled by a control value. The calibration loop may be configured to determine the control value that results in a given delay between the system clock and the second clock. The second phase interpolator circuit may be in a normal signal path and configured to generate a third clock with the given delay relative to the first clock using the control value such that the third clock is offset from the system clock by the given delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.