System, apparatus and method for dynamically controlling error protection features of a processor
US10437315B2 · kind B2 · utility
0Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2017 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Dec 27, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor core has one or more execution units, a first memory array having a first protection circuit to provide soft error protection to the first memory array, and a control circuit. A power controller coupled to the core may include a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the core to disable the first protection circuit. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.