Intelligent coded memory architecture with enhanced access scheduler
US10437480B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2015 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | May 23, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1647
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system, and architecture for efficiently accessing data in a memory shared by multiple processor cores that reduces the probability of bank conflicts and decreases latency is provided. In an embodiment, a method for accessing data in a memory includes determining, by a scheduler, a read pattern for reading data from memory to serve requests in a plurality of bank queues, the memory comprising a plurality of memory banks and a plurality of coding banks, the coding banks storing a coded version of at least some of the data stored in the plurality of memory banks; reading a first data from a first memory bank; reading coded data from one of the coding banks; and determining the second data according to the coded data and the first data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.